Embedded Technologies, Inc.

Serial FPDP (sFPDP)

Description

sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces with the most common option being 2.5 gigabits per second multimode fiber.

Product Specifications
  • Compliant with ANSI/VITA 17.1-2003 Serial FPDP standard

  • Supported link speeds

    • 1.0625 Gbaud
    • 2.125 Gbaud
    • 2.5 Gbaud

  • Data Frames supported

    • Unframed Data
    • Single Frame Data
    • Fixed Size Repeating Frame Data
    • Dynamic Size Repeating Frame Data

  • System Configurations supported

    • Basic System
    • Flow Control
    • Bi-directional Data Flow
    • Copy Mode
    • Copy/Loop Mode
  • Host-Bus interface

    • Parallel FPDP

  • Configurable parametersTransmit FIFO depth

    • Receive FIFO depth
    • Transmit FIFO watermark to assert SUSPEND output
    • Transmit FIFO watermark for TX FIFO Overflow signal generation

  • Receive FIFO watermark for STOP/GO signal generation

Highlights

  • Serial Front Panel Data Port (sFPDP) IP core for FPGA is based on the ANSI/VITA 17.1-2003 standard.
  • The Serial FPDP standard supports three data rates: 1.0625 Gbaud, 2.125 Gbaud, and 2.500 Gbaud.