Embedded Technologies, Inc.

Cyclone V SoC System On Module

Description

1 week Lead Time

iWave Systems launching Altera's Cyclone V SX SoC based Qseven compatible module for the increased system performance requirements. The Dual ARM Cortex A9 core with the FPGA allows greater flexibility for the system designers and helps to lower the system cost and power consumption. The improved logic integration with integrated high speed transceivers and hard memory controllers provides increased bandwidth capacity which is ideal for cost-sensitive high end applications.

Product Specifications
  • CPU:
    • Altera's Cyclone V SX SoC FPGA
    • Integrated Dual core ARM Cortex-A9 Hard Processor System(HPS)
    • FPGA with upto 110K LEs

  • Memory:
    • 512MB DDR3 with ECC for HPS
    • 16 MB QSPI Flash*
    • On-SOM Micro SD Connector#
    • 256MB DDR3 for FPGA
    • EPCQ flash* / QSPI Flash for FPGA
    • EEPROM*

  • On Board Peripherals  Support:
    • JTAG  Header  for FPGA*
    • JTAG Header for HPS*
    • DIP Switch for boot settings
    • RTC controller

  • 80 Pin Expansion Connector:
    • FPGA  IOs (Up to 45 Single Ended IOs - SE IOs)
    • 9 TX LVDS  Pairs / 18 SE IOs
    • 11 RX LVDS  Pairs / 22 SE IOs
    • 10 Single Ended IOs
    • 5 Single Ended IOs

  • FPGA Dedicated Clock IOs:
    • General Purpose Clock Inputs (2 LVDS/2 SE)
    • General Purpose Clock Output (1 LVDS/2 SE)

  • Others:
    • SMBUS / 2 SE IOs
    • FPGA JTAG

  • Operating Temperature: -40C to +85C Industrial
  • Qseven PCB Edge  Connector Interfaces:

  • From HPS:
    • Gigabit Ethernet - 1 Port (On-SOM PHY)
    • USB 2.0 Host - 4 Ports (On-SOM HUB)
    • CAN  - 1 Port
    • SD/MMC (8 bit) #
    • WDOG - 1 Port
    • I2C - 2 Ports
    • SPI - 1 Port
    • Debug  UART - 1 Port
    • 2nd UART  - 1 Port
    • Other Control IOs - Through HPS

  • From FPGA+:
    • LVDS LCD  - 2 Ports (FPGA Soft  IP)/ 23 SE IOs
    • AC97/I2S Audio (FPGA Soft  IP)/ 5 SE IOs
    • PWM
    • FPGA IOs - 8 SE IOs

  • From FPGA High Speed Transceivers+:
    • SATA (FPGA Soft  IP)
    • PCIe Gen1  x 4 Lane

  • OS Support:
    • Linux 3.10

  • Form Factor: 70mm x 70mm Qseven Specification 2.0

  • Power Input: 5V DC

  • REACH & RoHS Compliant

* Optional
# On-SOM Micro SD Connector and Qseven Edge SD/MMC are sharing the same interface
+If the FPGA interfaces available in the Qseven edge are not used for Qseven compliance requirement, same interface pins can be used for custom Industrial/networking interface requirements.

Highlights

  • ARM Cortex A9 Dual core CPU integrated with FPGA with up to 110K LEs
  • Enhanced with integrated transceivers and hard memory controller
  • Readily available FPGA IP cores for integration
  • R2.0 Qseven compatible module
  • First ARM based Qseven SOM module with PCIe x 4 lane support